RISC VS CISC

The simplest way to examine the advantages and disadvantages of RISC architecture is by contrasting it with it's predecessor: CISC (Complex Instruction Set Computers) architecture.
Multiplying Two Numbers in MemoryOn the right is a diagram representing the storage scheme for a generic computer. The main memory is divided into locations numbered from (row) 1: (column) 1 to (row) 6: (column) 4. The execution unit is responsible for carrying out all computations. However, the execution unit can only operate on data that has been loaded into one of the six registers (A, B, C, D, E, or F). Let's say we want to find the product of two numbers - one stored in location 2:3 and another stored in location 5:2 - and then store the product back in the location 2:3.
The CISC Approach The primary goal of CISC architecture is to complete a task in as few lines of assembly as possible. This is achieved by building processor hardware that is capable of understanding and executing a series of operations. For this particular task, a CISC processor would come prepared with a specific instruction (we'll call it "MULT"). When executed, this instruction loads the two values into separate registers, multiplies the operands in the execution unit, and then stores the product in the appropriate register. Thus, the entire task of multiplying two numbers can be completed with one instruction:
MULT 2:3, 5:2
MULT is what is known as a "complex instruction." It operates directly on the computer's memory banks and does not require the programmer to explicitly call any loading or storing functions. It closely resembles a command in a higher level language. For instance, if we let "a" represent the value of 2:3 and "b" represent the value of 5:2, then this command is identical to the C statement "a = a * b."
One of the primary advantages of this system is that the compiler has to do very little work to translate a high-level language statement into assembly. Because the length of the code is relatively short, very little RAM is required to store instructions. The emphasis is put on building complex instructions directly into the hardware.
The RISC Approach RISC processors only use simple instructions that can be executed within one clock cycle. Thus, the "MULT" command described above could be divided into three separate commands: "LOAD," which moves data from the memory bank to a register, "PROD," which finds the product of two operands located within the registers, and "STORE," which moves data from a register to the memory banks. In order to perform the exact series of steps described in the CISC approach, a programmer would need to code four lines of assembly:
LOAD A, 2:3LOAD B, 5:2PROD A, BSTORE 2:3, A
At first, this may seem like a much less efficient way of completing the operation. Because there are more lines of code, more RAM is needed to store the assembly level instructions. The compiler must also perform more work to convert a high-level language statement into code of this form.
Difference Between RISC and CISC::

• CISC
• Emphasis on hardware
• Includes multi-clockcomplex instructions
• Memory-to-memory:"LOAD" and "STORE"incorporated in instructions
• Small code sizes,high cycles per second
• Transistors used for storingcomplex instructionS
• RISC
• Emphasis on software
• Single-clock,reduced instruction only
• Register to register:"LOAD" and "STORE"are independent instructions
• Low cycles per second,large code sizes
• Spends more transistorson memory registers

However, the RISC strategy also brings some very important advantages. Because each instruction requires only one clock cycle to execute, the entire program will execute in approximately the same amount of time as the multi-cycle "MULT" command. These RISC "reduced instructions" require less transistors of hardware space than the complex instructions, leaving more room for general purpose registers. Because all of the instructions execute in a uniform amount of time (i.e. one clock), pipelining is possible.
Separating the "LOAD" and "STORE" instructions actually reduces the amount of work that the computer must perform. After a CISC-style "MULT" command is executed, the processor automatically erases the registers. If one of the operands needs to be used for another computation, the processor must re-load the data from the memory bank into a register. In RISC, the operand will remain in the register until another value is loaded in its place.
The Performance EquationThe following equation is commonly used for expressing a computer's performance ability:

The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction. RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program.
RISC Roadblocks Despite the advantages of RISC based processing, RISC chips took over a decade to gain a foothold in the commercial world. This was largely due to a lack of software support.
Although Apple's Power Macintosh line featured RISC-based chips and Windows NT was RISC compatible, Windows 3.1 and Windows 95 were designed with CISC processors in mind. Many companies were unwilling to take a chance with the emerging RISC technology. Without commercial interest, processor developers were unable to manufacture RISC chips in large enough volumes to make their price competitive.
Another major setback was the presence of Intel. Although their CISC chips were becoming increasingly unwieldy and difficult to develop, Intel had the resources to plow through development and produce powerful processors. Although RISC chips might surpass Intel's efforts in specific areas, the differences were not great enough to persuade buyers to change technologies.
The Overall RISC Advantage Today, the Intel x86 is arguable the only chip which retains CISC architecture. This is primarily due to advancements in other areas of computer technology. The price of RAM has decreased dramatically. In 1977, 1MB of DRAM cost about $5,000. By 1994, the same amount of memory cost only $6 (when adjusted for inflation). Compiler technology has also become more sophisticated, so that the RISC use of RAM and emphasis on software has become ideal.

TIGHTLY AND LOOSELY COUPLED SYSTEM

Tightly Coupled System
- Tasks and/or processors communicate in a highly synchronized fashion
- Communicates through a common shared memory
- Shared memory system
Loosely Coupled System
- Tasks or processors do not communicate in a
synchronized fashion
- Communicates by message passing packets
- Overhead for data exchange is high
- Distributed memory system

Target instructions prefetch

A processor that includes an execution pipeline that executes a programmed flow of instructions is provided. The processor also includes an instruction pointer generator configured to generate an instruction pointer. Furthermore, the processor includes a branch prediction circuit configured to receive the instruction pointer. In response to the instruction pointer, the branch prediction circuit is configured to determine if an instruction corresponding to the instruction pointer includes a branch that is predicted taken and if so to provide to said execution pipeline a target instruction corresponding to said instruction. The branch prediction circuit provides to the execution pipeline at least one target instruction corresponding to the instruction corresponding to the instruction pointer.

Throughput

In communication networks, such as Ethernet or packet radio, throughput is the average rate of successful message delivery over a communication channel. This data may be delivered over a physical or logical link, over a wireless channel, or that is passing through a certain network node, such as data passed between two specific computers. The throughput is usually measured in bits per second (bit/s or bps), and sometimes in data packets per second or data packets per time slot.
The system throughput or aggregate throughput is the sum of the data rates that are delivered to all terminals in a network.
The throughput can be analyzed mathematically by means of queueing theory, where the load in packets per time unit is denoted arrival rate λ, and the throughput in packets per time unit is denoted departure rate μ.

Throughput

In computer technology, throughput is the amount of work that a computer can do in a given time period. Historically, throughput has been a measure of the comparative effectiveness of large commercial computers that run many programs concurrently. An early throughput measure was the number of batch jobs completed in a day.

Throughput

Throughput is the rate at which a computer or network sends or receives data . It therefore is a good measure of the channel capacity of a communications link, and connections to the internet are usually rated in terms of how many bits they pass per second (bit/s)

System Call

A system call is a request made by any arbitrary program to the operating system for performing tasks -- picked from a predefined set -- which the said program does not have required permissions to execute in its own flow of execution. Most operations interacting with the system require permissions not available to a user level process, i.e. any I/O performed with any arbitrary device present on the system or any form of communication with other processes requires the use of system calls.

System Call

A system call is a request made by any arbitrary program to the operating system for performing tasks -- picked from a predefined set -- which the said program does not have required permissions to execute in its own flow of execution. Most operations interacting with the system require permissions not available to a user level process, i.e. any I/O performed with any arbitrary device present on the system or any form of communication with other processes requires the use of system calls.

Interrupts

An interrupt is an event in hardware that triggers the processor to jump from its current program counter to a specific point in the code. Interrupts are designed to be special events whose occurrence cannot be predicted precisely (or at all). The MSP has many different kinds of events that can trigger interrupts, and for each one the processor will send the execution to a unique, specific point in memory. Each interrupt is assigned a word long segment at the upper end of memory. This is enough memory for a jump to the location in memory where the interrupt will actually be handled. Interrupts in general can be divided into two kinds- maskable and non-maskable. A maskable interrupt is an interrupt whose trigger event is not always important, so the programmer can decide that the event should not cause the program to jump. A non-maskable interrupt (like the reset button) is so important that it should never be ignored. The processor will always jump to this interrupt when it happens. Often, maskable interrupts are turned off by default to simplify the default behavior of the device. Special control registers allow non-maskable and specific non-maskable interrupts to be turned on. Interrupts generally have a "priority;" when two interrupts happen at the same time, the higher priority interrupt will take precedence over the lower priority one. Thus if a peripheral timer goes off at the same time as the reset button is pushed, the processor will ignore the peripheral timer because the reset is more important (higher priority).

A two-phase-clock generator which generates a first clock and a nonoverlapping second clock from an input clock by utilizing gate delays, comprising:

a first floating inverter and a second floating inverter each having an input, an output, a first supply terminal and a second supply terminal, said input of said first logic gate and said input of said second logic gate being coupled to said input clock in antiphase, and said first supply terminals of each of said first and second floating inverters connected to a supply voltage;

a first output buffer having an input coupled to said output of said first floating inverter and having an output that provides said first clock, said output further being provided as feedback to said second supply terminal of said second floating inverter; and

a second output buffer having an input coupled to said output of said second floating inverter and having an output that provides said nonoverlapping second clock, said output further being provides as feedback to said second supply terminal of said first floating inverter.

A two-phase clock generator generates a nonoverlapping two-phase clock from a unipolar input clock by utilizing gate delays in first and second signal paths. The output of each signal path is fed over a cross-coupled feedback path back to a logic gate in the respective other signal path. Each logic gate is a floating inverter having a first supply terminal connected to a supply voltage, and having a second supply terminal that is the feed point for the respective feedback signal from the output of the other signal path.

ADDRESSING METHODS

ADDRESSING METHODS


ABSOLUTE (DIRECT) ADDRESSING

- The address of operand is given explicity as part of the instruction



IMPLIED ADDRESSING

- The address is implied by the instruction (e.g.,in one-address machine, the address
of the second operand is implied as being accumulator)


IMMEDIATE ADDRESSING

- The operand is given explicitly as the instruction. No memory
access is required. Also operand could follow immediately after the instruction.


INDIRECT ADDRESSING
- The effective address of the operand is in the register or main memory location
whose address appears in the instruction. It can have more than one level.


INDEXED ADDRESSING
- The effective address (EA) of the operand is generated by adding an index register
value (X) to the direct address (DA)
- EA = X + DA


BASE ADDRESSING

- The effective address of the operand is generated by adding base register value (B)
to the address
- EA = B + DA
CA - IV - D&IF - 16


SELF-RELATIVE ADDRESSING

- Effective address is a sum of a direct address and a program counter contents (PC).
EA = DA + PC


AUGMENTED ADDRESSING

- Effective address is a concatenation of the contents of the augmented address
register (AAR) and direct address.
EA = AAR || DA
(AAR often specifies a page and DA is an address within this
particular page)


BLOCK ADDRESSING

- Address of the first word in the block is given. Length of the block is usually specified
in the instruction; or also the last address can be given; or special end-of-block
character can be given; or blocks may have fixed length. Very useful in the
secondary storage management.

INTERRUPTS

see this to know about interrupts: http://en.wikipedia.org/wiki/Interrupt

IMPLEMENTATIONS OF SYSTEM CALLS

Typical implementations
Implementing system calls requires a control transfer which involves some sort of architecture specific feature. A typical way to implement this is to use a software interrupt or trap. Interrupts transfer control to the kernel so software simply needs to set up some register with the system call number they want and execute the software interrupt.
For many RISC processors this is the only feasible implementation, but CISC architectures such as x86 support additional techniques. One example is SYSCALL/SYSRET which is very similar to SYSENTER/SYSEXIT (the two mechanisms were created by Intel and AMD independently, but do basically the same thing). These are "fast" control transfer instructions that are designed to quickly transfer control to the kernel for a system call without the overhead of an interrupt. Linux 2.5 began using this on the x86, where available; formerly it used the INT instruction, where the system call number was placed in the EAX register before interrupt 0x80 was executed.[1]
An older x86 mechanism is called a call gate and is a way for a program to literally call a kernel function directly using a safe control transfer mechanism the kernel sets up in advance. This approach has been unpopular, presumably due to the requirement of a far call which uses x86 memory segmentation and the resulting lack of portability it causes, and existence of the faster instructions mentioned above.

INTERRUPT:

An interrupt is an event in hardware that triggers the processor to jump from its current program counter to a specific point in the code. Interrupts are designed to be special events whose occurrence cannot be predicted precisely .

TYPES:

In general ,interrupt can be divided into two kinds- maskable and non-maskable.

A maskable interrupt is an interrupt whose trigger event is not always important, so the programmer can decide that the event should not cause the program to jump.

A non-maskable interrupt (like the reset button) is so important that it should never be ignored. The processor will always jump to this interrupt when it happens.

what is a system call

A system call is a request made by any arbitrary program to the operating system for performing tasks -- picked from a predefined set -- which the said program does not have required permissions to execute in its own flow of execution. Most operations interacting with the system require permissions not available to a user level process, i.e. any I/O performed with any arbitrary device present on the system or any form of communication with other processes requires the use of system calls..........

The OS executes at the highest level of privilege and allows the applications to request services via system calls, which are often implemented through interrupts. If allowed, the system enters a higher privilege level, executes a specific set of instructions which the interrupting program has no direct control over, then returns control to the former flow of execution. This concept also serves as a way to implement security......

interrupt service

An interrupt service routine (ISR) is a software routine that hardware invokes in response to an interrupt. ISRs examine an interrupt and determine how to handle it. ISRs handle the interrupt, and then return a logical interrupt value. If no further handling is required because the device is disabled or data is buffered, the ISR notifies the kernel with a SYSINTR_NOP return value. An ISR must perform very fast to avoid slowing down the operation of the device and the operation of all lower priority ISRs.
Although an ISR might move data from a CPU register or a hardware port into a memory buffer, in general it relies on a dedicated interrupt thread, called the interrupt service thread (IST), to do most of the required processing. If additional processing is required, the ISR returns a logical interrupt value, other than SYSINTR_NOP, to the kernel. It then maps a physical interrupt number to a logical interrupt value.

INTERRUPT

A signal informing a program that an event has occurred. When a program receives an interrupt signal, it takes a specified action (which can be to ignore the signal). Interrupt signals can cause a program to suspend itself temporarily to service the interrupt.
Interrupt signals can come from a variety of sources. For example, every keystroke generates an interrupt signal. Interrupts can also be generated by other devices, such as a printer, to indicate that some event has occurred. These are called hardware interrupts. Interrupt signals initiated by programs are called software interrupts. A software interrupt is also called a trap or an exception.
PCs support 256 types of software interrupts and 15 hardware interrupts. Each type of software interrupt is associated with an interrupt handler -- a routine that takes control when the interrupt occurs. For example, when you press a key on your keyboard, this triggers a specific interrupt handler. The complete list of interrupts and associated interrupt handlers is stored in a table called the interrupt vector table, which resides in the first 1 K of addressable memory.
Also see the list of IRQ numbers in the Quick Reference section of Webopedia

INTERRUPT

A signal informing a program that an event has occurred. When a program receives an interrupt signal, it takes a specified action (which can be to ignore the signal). Interrupt signals can cause a program to suspend itself temporarily to service the interrupt.
Interrupt signals can come from a variety of sources. For example, every keystroke generates an interrupt signal. Interrupts can also be generated by other devices, such as a printer, to indicate that some event has occurred. These are called hardware interrupts. Interrupt signals initiated by programs are called software interrupts. A software interrupt is also called a trap or an exception.
PCs support 256 types of software interrupts and 15 hardware interrupts. Each type of software interrupt is associated with an interrupt handler -- a routine that takes control when the interrupt occurs. For example, when you press a key on your keyboard, this triggers a specific interrupt handler. The complete list of interrupts and associated interrupt handlers is stored in a table called the interrupt vector table, which resides in the first 1 K of addressable memory.
Also see the list of IRQ numbers in the Quick Reference section of Webopedia

Interrupt

In computing, an interrupt is an asynchronous signal from hardware indicating the need for attention or a synchronous event in software indicating the need for a change in execution. A hardware interrupt causes the processor to save its state of execution via a context switch, and begin execution of an interrupt handler. Software interrupts are usually implemented as instructions in the instruction set, which cause a context switch to an interrupt handler similar to a hardware interrupt. Interrupts are a commonly used technique for computer multitasking, especially in real-time computing.
An act of interrupting is referred to as an interrupt request

Microprogram

: A sequence of microinstructions that are in special storage where they can be dynamically accessed to perform various functions.

FUNCTIONS OF CONTROL UNIT

Functions!!!
The ControL Unit can be thought of as the brain of the CPU itself. It controls based on the instructions it decodes, how other parts of the CPU and in turn, rest of the computer systems should work in order that the instruction gets executed in a correct manner. There are two types of control units, the first type is called hardwired control unit. Hardwired control units are constructed using digital circuits and once formed cannont be changed. The other type of control unit is microprogrammed control unit. A microprogrammed control unit itself decodes and execute instructions by means of executing microprograms.

CISC AND RISC ARCHITECTURE

CISC Architecture:
CISC (Complex Instruction Set Computer) architecture means hardwiring( directly wired into a computer or physically connected to a computer system or network) the processor with complex instructions that are difficult to create using basic instructions.

CISC is especially popular in 80x86 type processors. This type of architecture has an elevated cost because of advanced functions printed on the silicone.

Instructions are of variable length and may sometimes require more than one clock cycle. Because CISC-based processors can only process one instruction at a time, the processing time is a function of the size of the instruction.

RISC Architecture:
Processors with RISC (Reduced Instruction Set Computer) technology do not have hardwired, advanced functions.

Programs must therefore be translated into simple instructions which complicates development and/or requires a more powerful processor. Such architecture has a reduced production cost compared to CISC processors.

In addition, instructions, simple in nature, are executed in just one clock cycle, which speeds up program execution when compared to CISC processors. Finally, these processors can handle multiple instructions simultaneously by processing them in parallel.

Parallel Processing

Parallel Processing:
Parallel processing consists of simultaneously executing instructions from the same program on different processors. This involves dividing a program into multiple processes handled in parallel in order to reduce execution time.

CONTROL MEMORY

Microprogram control

Microprogrammed Control
The control signals needed in each step of intruction execution can be generated by the finite state machine method, also called hardwired control, or, alternatively, by the microprogrammed control method discussed below.
Basic Concepts of Microprogramming:
Control word (CW):
A word with each bit for one of the control signals. Each step of the instruction execution is represented by a control word with all of the bits corresponding to the control signals needed for the step set to one.
Microinstruction:
Each step in a sequence of steps in the execution of a certain machine instruction is considered as a microinstruction, and it is represented by a control word. All of the bits corresponding to the control signals that need to be asserted in this step are set to 1, and all others are set to 0 (horizontal organization).
Microprogram:
Composed of a sequence of microinstructions corresponding to the sequence of steps in the execution of a given machine instruction.
Microprogramming:
The method of generating the control signals by properly setting the individual bits in a control word of a step.

Two phase clock generator

APPLICATIONS OF LOGIC MICROOPERATIONS

Selective-set Operation

Used to force selected bits of a register into logic-1 by using the OR operation

Example: 0100 ? 1000 = 1100


Selective-complement (toggling) Operation

Used to force selected bits of a register to be complemented by using the XOR operation

Example: 0001 ? 1000 = 1001

APPLICATIONS OF LOGIC MICROOPERATIONS

Set (Preset) Microoperation:

Force all bits into 1’s by ORing them with a value in which all its bits are being assigned to logic-1
Example: 100110 ? 111111 = 111111


Clear (Reset) Microoperation:

Force all bits into 0’s by ANDing them with a value in which all its bits are being assigned to logic-0
Example: 100110 ? 000000 = 000000

Defn microoperation & APPLICATIONS OF LOGIC MICROOPERATIONS

•The operations on the data in registers are called microoperations.





APPLICATIONS OF LOGIC MICROOPERATIONS


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DESCRIPTION OF TRI-STATE BUFFER

A tri-state buffer is a useful device that allows us to control when current passes through the device, and when it doesn't. A tri-state buffer has two inputs: a data input x and a control input c. The control input acts like a valve. When the control input is active, the output is the input. That is, it behaves just like a normal buffer. The "valve" is open.
When the control input is not active, the output is "Z". The "valve" is open, and no electrical current flows through. Thus, even if x is 0 or 1, that value does not flow through.